1. Technical Field
The present invention relates to software tools in general, and, in particular, to a software tool for verifying memory testing software. Still more particularly, the present invention relates to a method and apparatus for verifying the accuracy of logical-to-physical mapping software.
2. Description of Related Art
Conceptually speaking, diagnosing failures in a memory device is fairly straightforward. Basically, after a memory tester has detected a failure in a memory device, the logical address of the failed memory location is translated into a corresponding physical location within the memory device. Such translation is commonly known as a logical-to-physical translation and is typically performed by a logical-to-physical mapping software. Once the failed physical location of the memory device is known, different analyses can be performed. For example, photographic data of the memory device can be compared to the physical location obtained by a tester to determine whether or not they correlate to the same location.
Methods for obtaining failed logical addresses of memory devices during memory testings are well-known in the art. For stand-alone memory devices, the logical addresses are already known by memory testers. For memory devices utilizing built-in self-test (BIST), several schemes have been developed for translating what memory testers know (typically in cycle numbers) into corresponding logical addresses.
The major problem in memory testings lies upon the inability to verify whether or not the logical-to-physical mapping software is functioning correctly. There are several points within the logical-to-physical mapping software at which errors can be introduced. For example, memory designers may mis-communicate the logical-to-physical algorithm description to software engineers who write the logical-to-physical mapping software. Also, the cycle delays from the time a memory fail occurred to the time the memory fail being detected are usually not accounted for. In addition, during a cycle in which a memory tester observed the fail, test data are not corrected for cycle offsets due to counters (such as whether it starts at 0 or 1) and for any operations that take place before memory test begins (e.g., a “reset” operation).
The prior art solution to the above-mentioned problem is to test memory devices that come off a manufacturing line early in the life of the process (often as a special-purpose test chip) and generate a bit-fail map (BFM) of the failing memory cells. Memory designers then look at the BFM and identify the likely locations for a physical defect that could cause the memory failure. The failed memory device is then sent to failure analysis where it is stripped down to the circuit layers that include the memory and then the locations identified by the memory designers are observed. If an abnormality is found, it is assumed that the abnormality is a defect that caused the memory failure. With such methodology, however, only by physically observing multiple defects with high accuracies can any level of confidence be achieved. In practice, frequently no defect is observed at the location that casts doubt on the logical-to-physical mapping software.
Consequently, it would be desirable to provide an improved method for verifying logical-to-physical mapping software that is convenient and relatively inexpensive to implement.